1. Technical Field
A method of reading a flash and a NAND type flash memory device is disclosed wherein a plurality of page buffers are divided into predetermined groups and are then sequentially driven on a group basis to prevent erroneous operation due to excessive power consumption.
2. Description of the Related Art
There is an increasing demand for semiconductor memory devices in which electrical programming and erase are allowed, and where a refresh function of rewriting data at a constant cycle is not required. Further, in order to develop large-capacity memory devices capable of storing a large amount of data, the integration of memory cells has been increased. In order to fulfill the higher integration of the memory cells, a NAND type flash memory device has been developed in which a plurality of cells are serially connected to form one string and two strings share one contact. Program and erase of the NAND type flash memory device are performed by controlling a threshold voltage of a memory cell, while injecting or discharging electrons into or from a floating gate by way of F-N tunneling.
Accordingly, an erased cell has a negative threshold voltage since electrons of the floating gate are discharged. A programmed cell has a positive threshold voltage since electrons are injected into a floating gate. In case of the NAND type flash memory device, failure occurs due to charge gain or charge loss. A variety of verification schemes with respect to these characteristics has been developed. In order to perform a read operation for a verifying normal program and erase or store data program, a page buffer is used.
The page buffer temporarily stores data to be stored in a memory cell of a selected page, which is connected to a string of a memory cell array, or reads the status of a cell by sensing and amplifying information on a memory cell of a selected page.
In order to read information on a selected cell of a NAND type flash memory device, all page buffers within one chip must be driven at the same time, and all word lines of a selected block must be enabled. In this state, one cell is selected according to a signal for selecting a cell, and information on the cell is read. At this time, since all word lines of a selected block are enabled, current flows from the page buffer to the cell. If all page buffers of 2 k+64 Byte operate and a highest current flows, an instant peak current becomes too high, which causes power-down to occur within a chip. This results in erroneous operation of a chip. Meanwhile, the peak current increases as the number of page buffers that operate at the same time increases.